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PIC16F946
DS41265A-page 142
Preliminary
2005 Microchip Technology Inc.
11.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
When setting up an Asynchronous Reception with
address detect enabled:
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit RCIE.
Set bit RX9 to enable 9-bit reception.
Set ADDEN to enable address detect.
Enable the reception by setting enable bit CREN.
Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
If any error occurred, clear the error by clearing
enable bit CREN.
If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
FIGURE 11-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop
Start
(8)
7
10
RX9
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
FOSC
SDI/SDA/SEG8
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